1. Field of the Invention
The present invention is related to compiler/translator methods, systems and programs, and more specifically to techniques for supporting predication in out-of-order processors by generating code having symmetrically placed write operations and indications of their conditional execution path associations.
2. Description of Related Art
Out-of-order instruction processing architectures are prevalent in present-day processors and provide efficient use of available processing resources. By not rigidly restricting the order in which groups of instructions (or individual instructions) are decoded and/or executed, processing resources can be used more efficiently, resulting in either greater computation power, or reduced intervals in which a processing system must be operated out of standby or other power-conserving mode. However, when the processing of a particular instruction is “predicated” on the results of a conditional instruction, without additional predication logic, the processor must typically stall waiting for the condition to be resolved prior to executing the particular instruction. Predication support logic provides mechanisms for avoiding the stall requirement, but the inclusion of predication support complicates the processor logic greatly. Static predication, in which the compiler specifically delineates regions of program code as belonging to different conditional paths, solves the problem of stalling, but requires additional resources and logic to discard instructions and/or results associated with “not-taken” instruction paths and to resolve the dependencies of values on the conditional branches to the “taken” path results. Also, static predication typically requires that each instruction of the instruction set architecture (ISA) have a mechanism, such as an operand or field that provides the path association information. Not all ISAs provide such support and it is a non-trivial problem to include such support in ISAs.
Typical predication logic tracks instructions through various pipelines in the processor and ensures that if a potentially invalid result is computed by relying on a value that was determined from a condition that was not properly resolved at the time of computation, the potentially invalid result can be replaced. Special tags are used to indicate that a value is bifurcated and that a final register or memory value is split between two or more possible results. The flag causes the processor logic to avoid committing the result until the branch or other dependency is finally resolved. The logic and resources to accomplish the above-described predication handling are generally centered around the register renamer, the issue unit, the write-back unit and the completion unit, as the rename process generates ambiguous locations that each represent a possible result of execution and the proper result must be identified and resolved to the final register/memory location. The rename process described above also requires additional rename resource when handling predicated values in out-of-order execution, since multiple rename registers must be used to represent the same value. Some predication techniques insert special instructions to merge the results from the conditional paths, and other techniques provide additional levels of indirection to handle ambiguous values, thereby introducing machine overhead in non-predicated instruction handling, as well.
Therefore, it would be desirable to handle predication in an out-of-order processor without requiring complex logic, an increased number of rename resources, or stalling instruction decoding/dispatching until conditions that control dependencies are resolved.